1. Field of the Invention
The present invention relates to a semiconductor device, a method of forming a semiconductor device, and a data processing system.
Priority is claimed on Japanese Patent Application No. 2010-115538, May 19, 2010, the content of which is incorporated herein by reference.
2. Description of the Related Art
Recently, dimensions of transistors have become smaller due to miniaturization of semiconductor elements. The dimensional reductions of the transistors will cause remarkable short channel effects of the transistors. As the dimensions of memory cells in dynamic random access memories (DRAMs) and the like are reduced, the channel lengths of transistors are also reduced, which may cause degradation of the performance of transistors. The deterioration in retention of memory cells or writing characteristics has been problematic.
In view of the above, recess (trench) field effect transistors (FETs), fin FETs, and the like have been developed. The recess (trench) FET has a structure in which a trench (also called a groove) is formed in a semiconductor substrate to obtain a channel having a three-dimensional structure. Japanese Unexamined Patent Application, First Publications, Nos. JP-A-2005-064500, JP-A-2007-027753, and JP-A-2007-305827 disclose that the fin FET has a structure in which a fin is formed between trenches to obtain a channel having a three-dimensional structure.
The trench FET is formed by forming a trench in a semiconductor substrate and forming a gate electrode within the trench while a gate insulating film is interposed between the gate electrode and the semiconductor substrate. A channel of the trench FET has a three-dimensional structure. The fin FET is formed by forming a gate electrode over a gate insulting film so as to cross over a fin protruding from a bottom surface of the trenches formed in the semiconductor substrate. Consequently, the channel has a three-dimensional structure. In any case, it is possible to suppress the short channel effects because the gate length can be lengthened with respect to the channel width.
A study has been carried out to adopt buried gate transistors for selecting transistors included in memory cells in the DRAMs due to reduction in size of the memory cell. The buried gate transistor has a structure in which a gate electrode is buried in the semiconductor substrate.
The gate electrode of the buried gate transistor does not protrude from the surface of the substrate because the gate electrode (word line) is buried in the semiconductor substrate. Among wirings connected to memory cells, only bit lines are located over the semiconductor substrate. This will increase flexibility of layouts of capacitors, contact plugs, and the like, which are included in the memory cell and formed over the semiconductor substrate. This will reduce the difficulty of processing the capacitors, the contact plugs, and the like.